1. Field of the Invention
This invention relates to a method for making sealed cavities on silicon wafer surfaces with electrically insulated conductors through sealing areas to connect functional devices inside the cavities electrically to electrical terminals outside said cavities. This method of making sealed cavities can be performed on wafer level to meet requirements for low-cost batch processing. The method is in particular well suited for building silicon sensors such as pressure sensors which include reference volumes with controlled atmosphere or vacuum and sensors which include vibrating resonating structures with vacuum reference volumes as an integral part of the die structure, as well as force sensors such as accelerometers which include features such as mechanical overload protection and squeeze film damping. The method also provides a good alternative for micropackages on the chip level for the protection of delicate structures such as surface micromachined structures, against the environment, thereby allowing low-cost plastic packaging to be used instead of expensive metal or ceramic packages.
The invention also relates to a sealed cavity device made by the inventive method.
2. Description of Related Prior Art
Silicon microsensors and microsystems are of increasing importance and will be subject to fast growth. Silicon pressure sensors are already elements of important industrial production and new types of sensors such as silicon accelerometers and silicon flow sensors are now subject to a growing market. Within the area of microactuators ink jet nozzles, fuel injection nozzles and micropumps built from single crystal silicon are already on the market. In the future many new products will be developed and brought on the market not only within the field of sensors and microactuators, but also complete microsystems with sensors, microactuators and electronics on the same single silicon chip will soon be a reality. A limiting technological factor for industrial growth within this field of technology is the complexity and high costs related to sensor assembly and packaging technology. It is the view of the inventors that new methods for assembly of such true 3-dimensional structures will be needed. Such assembly methods should be performed on the wafer level to reduce assembly and packaging cost and should result in high reliability devices and microsystems. Methods to provide sealed cavities on a surface of silicon and with electrical connections extending over the sealing area for connecting functional devices inside the cavity with the outside is today very limited. New methods are therefore needed for high-reliability and high accuracy sensors such as absolute pressure sensors, microaccelerometers and devices that are using resonant structures with high Q-factor. An overview of methods for micromachining of three dimensional structures in silicon is given by Kendall et. al: "Critical Technologies for the Micromachining of Silicon"; Semiconductors and Semimetals, Vol 1.37 (1992).
Below is a discussion of some important industrial prior art processes and methods that are available for sealing wafers together, in the following referred to as wafer lamination processes.
Eutectic bonding by the use of gold-silicon is a well known method that has been used for assembly of silicon dies for many years. The method has also been tried for silicon to silicon wafer bonding by using a deposited thin gold film on the surface of one of the wafers, but this method suffer from the following important drawbacks. A first limitation is due to the fact that gold is a fast diffuser in silicon and the method can therefor not be used in areas of PN-junctions at or near the surface since the penetration of gold will cause electrical shorts and high leakage currents between conductors. A second limitation is due to the large differences in thermal expansion coefficient, viz. 13.times.10-6 ppm/degC. for eutectic gold-silicon and 2.6.times.10-6 ppm/degC. for silicon, yielding high stress in the seal. A third drawback is due to the fact that gold-silicon eutectic bonding is very sensitive to the thin native oxides that always are present on silicon surfaces, thus, necessitating scrubbing action to make the eutectic melt to form and making complete sealing over large areas difficult.
Soldering is also used for assembly of silicon dice to silicon or other materials to make sensors as described by Yamada el. al. in U.S. Pat. No. 4,023,562. Such a process may be used to assemble parts together on the die level, but is difficult to control as a high yield process for assembly of all the dice on a wafer on the wafer level due to difficulties in obtaining uniform soldering of fine patterns over large areas. Yamada et. al. use Au--Sn eutectic solder. Another disadvantage of this prior art method is the high built-in stress due to the use of a brittle hard solder material with a large difference between thermal expansion 16.times.10-6 ppm/degC. for Au--Sn and 2.6.times.10-6 ppm/degC. for silicon.
Another method that has been used for many years is the use of glass as sealing material to seal silicon to silicon, including glasses that can be printed in the form of a paste. An example of such prior art is European patent publication 0127176. The use of this prior art method has so far mainly been limited to back-side sealing only where no electrical connections are present and needed.
Anodic bonding of glass to silicon is a method of increasing use for wafer bonding and wafer lamination by the use a glass with a thermal expansion coefficient well matched to that of silicon. Examples of such glasses are Pyrex 7740 from Corning, TEMPAX from Schott/DESAG and SD2 from Hoya. An overview of anodic bonding as method is given by K. B. Albaugh and P. E. Cade: "Mechanism of Anodic Bonding of Silicon to Pyrex Glass"; Tech. Digest, IEEE Solid State Sensor and Actuator Workshop, Hilton Head Island, S.C., 1988, p. 109 and by Bengtson: "Semiconductor Wafer Bonding: A Review of Interfacial Properties and Applications"; Journal of Electronic Materials, Vol. 21, No. 8, 1992 pp. 841-862. A good example of the prior art relating to how anodic bondable glass substrates are used to make pressure sensors is described by Yamada et. al. in European Patent Publication 0127176, according to which pyrex substrate is bonded to the unpatterned back-side of a pressure sensor for a support and pressure inlet function and not in the area of the silicon with electrically active parts and PN-junctions. This method is also used to form vacuum reference volumes under the silicon diaphragm on the side opposite to the side of the silicon chip containing electrical connections. Anodic bonding can also be performed by the use of sputtered thin glass films deposited on a silicon substrate. This method is described by Hanneborg et. al: "Anodic Bonding of Silicon Chips Using Sputter-deposited Pyrex 7740 Thin Films"; Proceeding of the 12.th Nordic Semiconductor Meeting, Jevnaker, June 8-11, pp. 290-293, ISBN 82-7267-858-6. Silicon-to silicon assemblies by using sputtered pyrex films are characterized by very low built-in stress resulting in sensors of very good long-term stability as described by Hanneborg et. al.: "An Integrated Capacitive Pressure Sensor with Frequency Output"; Sensors and Actuators, 9 (1986) pp. 345-361 and by Holm et. al.: "Stability and Common Mode Sensitivity of Piezoresistive Silicon Pressure Sensors made by different Mounting Methods"; Digest of Technical Papers of Transducers '91, San-Francisco, pp. 978-991. Anodic bonding is also demonstrated for vacuum packaging of microsensors by Henmi et. al.: "Vacuum Packaging for Microsensors by Glass-Silicon Anodic Bonding"; Proceeding from The 7th International Conference on Solid-State Sensors and Actuators, pp. 584-587.
A method of building sealed cavity structures in pressure sensors is presented by Yamada et. al. in U.S. Pat. No. 4,291,293 where a glass cover is sealed against a thin poly-silicon film in the surface area of the silicon chip that includes diffused crossing conductors on the silicon surface and with passivation between the single crystal silicon surface and the poly-silicon film in the sealing area. The inventors herein have, however, recognized the following limitations and drawbacks of this prior art. Anodic bonding to poly-silicon surfaces is difficult on large areas due to the surface roughness and inclusions that is common for poly-silicon films, thus making the method more suitable for anodic bonding on the die level rather than on the wafer level. Another important technological problem with this prior art method is the difficulty of avoiding mobile ions from the anodic bonding glass to drift through the poly-silicon film and into the passivating film at the bonding temperature, thereby causing electrical instability and reliability problems. This problem of prior art is illustrated in FIG. 1(a) and 1(b). FIG. 1(a) shows a small cross-sectional part of the sealing area of the prior art according to U.S. Pat. No. 4,291,293 before the sealing of the glass and shows the poly-silicon layer 424 on top of the passivation 423 and with one diffused P-type crossing conductor 442 and with the insulating space-charge region 440 of the pn-junction 443 extending into the p-side to the line 444 and into the N-type substrate area 426 to line 445. With no ions in the passivating film 423 the space-charge region 440 will extend with uniform thickness all around the p-conductor including the surface area. FIG. 1(b) shows the same structure after anodic bonding with the glass 415 bonded to the surface of the poly-silicon layer 424. During the anodic bonding process that takes place at about 300-450 degC., sodium ions Na+ drift from the glass through the poly-silicon film 424 and into the passivation layer 423. An accumulation layer of electrons 446 will form on the surface of the lightly doped N-type silicon part 426 leading to a reduction in the width of the insulating space-charge region 440 at the surface 447, thereby resulting in a reduction in insulation-to-withstand-voltage and electrical break-down of the junction will thus occur at a reduced voltage. Such effects may lead to non-functional devices after anodic bonding turning out as a yield problem, and this effect may also cause destructive failures during operation in the field due to the mobile nature of the Na+ ions in the passivation. Ionic contamination in the passivation over PN-junctions may not only lead to reduction in break-down voltages and cause leakages currents, but may also cause N-type inversion layers to be formed on lightly doped P-type areas between doped N-areas that should be insulated from each other. Such effects are well known for persons with knowledge in the field of semiconductor physics and are among others described in a semiconductor textbook by A. S. Grove: "Physics and Technology of Semiconductor Devices", Chapter 10, 11 and 12; John Wiley & Sons, Inc. (1967).